This invention relates to a technique and structure for producing very high resolution color images using a monochrome charge-coupled device (CCD) imager and a sequential color illumination scheme.
Conventional schemes for obtaining color electronic snapshots have traditionally employed one of three techniques. The first of these techniques uses white light illumination of a color CCD imager (FIG. 1). A color CCD imager 10 comprises a monochrome CCD imager upon which color sensitive stripes 14, 16, and 18 are deposited resulting in a mosaic of color pixels 12. The stripes are generally photo sensitive to alternating complementary colors such as red, green, and blue.
The second technique uses white light illumination of a color CCD imaging module. As illustrated by FIG. 2, a color CCD imaging module 20 employs three monochrome CCD imagers 22, 24, and 26 placed behind a beam-splitter 28. The beam-splitter separates the incoming radiation 30 into three beams of different spectral bands (typically, red 32, green 34, and blue 36), with each imaging module storing one of the monochrome images. Both of these techniques can be used to obtain snapshots of subject matter with brief exposure time (e.g., moving objects), however the cost is considerable.
A third technique, as shown in FIG. 3, employs a system 40 which uses a monochrome CCD imager with a sequential color illumination scheme. A filter wheel 42 is rotated in front of the imager 44 or the light source 46 so that the imager is exposed to a series of the color images which are then read out sequentially. This technique is less expensive than the previously described techniques, but has limitations in the subject matter for which it can be used. Because the monochrome imager is generally exposed to three color images sequentially, the exposure time for obtaining a complete image is often longer than that required for the other techniques.
This problem is aggravated by the fact that the preferred CCD imager architecture for very high resolution color snapshots is the full frame architecture. The full frame architecture provides the highest pixel density but at the cost of maintaining a storage area. As a result of the fact that there is no storage area, image integration and readout times have to be successive rather than simultaneous as with other architectures used, for example, in video applications. Because of the need to shield the imager during successive image read-outs the total exposure time must include three integration times (one for each color) and two read-out times.
FIG. 4 shows a timing diagram which is representative of a typical exposure time. The top time line 47 is the integration time line which indicates when the CCD imager is exposed to an image. The middle time line 48 is the read-out time line which indicates when a stored image is being read out. The bottom time line 49 is the total exposure time line which represents the time required to acquire a complete color image.
At t.sub.1, the imager is exposed to the blue portion of the image (integration time line 47). The image stored during the exposure is then read out beginning at time t.sub.2 (read-out time line 48). After the image is downloaded, the imager is exposed to the red portion of the image at t.sub.3. The red portion of the image is then downloaded at time t.sub.4. Finally, at t.sub.5 the imager is exposed to the green portion of the image which is read out at t.sub.6. Thus, as illustrated on the total exposure time line 49, this imaging scheme requires three exposures and two read-out intervals before a complete color image can be obtained. In addition, the high density of pixels and sequential nature of the downloading of imaging information further increases the total exposure time, often taking as long as five to ten seconds for a complete color image to be stored. The result being that this technique is unsuitable for creating images of moving subject matter.
FIG. 5 shows a simplified representation of a conventional three-phase full frame CCD imager 50 which can be used with any of the above-described techniques. Three gate electrodes 52 of each individual semiconductor storage cell 54 (one such cell shown outlined in bold lines) are controlled by one set of clock signals o.sub.1, o.sub.2, and o.sub.3. Charge which is stored in each row of cells is shifted into a horizontal CCD register 56 from which it can be read out serially through output 58.
In light of the preceding discussion, it is apparent that there exists a need for a full frame, color CCD imager which combines the low cost of sequential color illumination with the speed of costly white light illumination schemes.